FPGA Design Flow with Automated Test Generation
نویسندگان
چکیده
A novel FPGA design flow combined with automated hierarchical test pattern generation was developed and experimented on a real FPGA circuit for telecommunication. A hierarchical test generator for digital systems described in VHDL is presented. Both, register-transfer (RT) and gate level descriptions are used. Decision diagrams are exploited as a uniform model for describing systems at both levels. The method combines bottom-up and top-down approaches to make hierarchical test generation more efficient. It combines RT level deterministic test planning with gatelevel local test generation based on deterministic approach at the bottom-up working mode or on random approach at the top-town working mode. Experimental results have shown the advantages of using structural tests generated by ATPG compared to using functional test sequences created by designer.
منابع مشابه
Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose
FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs because there is no efficient method to authenticate the originality of bitstream by the FPGA pr...
متن کاملA Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD Flow
We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized ...
متن کاملSynthesis of FPGA Implementations from Loop Algorithms
We consider the problem of automatically mapping computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that all...
متن کاملAutomatic hardware generation for the Molen reconfigurable architecture: a G721 case study
The advantages of the reconfigurable technology in terms of performance have been widely recognized. However, programming reconfigurable systems and designing hardware accelerators for them is not a trivial task. The Molen paradigm provides an easy to use approach to couple a General Purpose Processor (GPP) with custom designed reconfigurable accelerators both at program level and at hardware d...
متن کاملAutomated flow for compressing convolution neural networks for efficient edge-computation with FPGA
Deep convolutional neural networks (CNN) based solutions are the current stateof-the-art for computer vision tasks. Due to the large size of these models, they are typically run on clusters of CPUs or GPUs. However, power requirements and cost budgets can be a major hindrance in adoption of CNN for IoT applications. Recent research highlights that CNN contain significant redundancy in their str...
متن کامل